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M32C/8A Group
RENESAS MCU
REJ03B0213-0110 Rev.1.10 Jul 15, 2007
1.
1.1
Overview
Features
The M32C/8A Group is a single-chip control MCU, fabricated using high-performance silicon gate CMOS technology, embedding the M32C/80 Series CPU core. The M32C/8A Group is housed in 144-pin and 100-pin plastic molded LQFP packages. With a 16-Mbyte address space, this MCU combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed. The M32C/8A Group has a multiplier and DMAC adequate for office automation, communication devices and industrial equipment, and other high-speed processing applications.
The M32C/8A Group is ROMless device. Use the M32C/8A Group in microprocessor mode after reset.
1.1.1
Applications
Audio, cameras, office/communication/portable equipment, etc.
1.1.2
Specifications
Tables 1.11.3 to 1.4 lists the specifications of the M32C/8A Group.
Rev.1.10
Jul 15, 2007
Page 1 of 65
M32C/8A Group Table 1.1 Item CPU Specifications (144-Pin Version) (1) Function Central processing unit
Specification M32C/80 core (multiplier: 16 bits x 16 bits 32 bits, multiply-addition operation instructions: 16 x 16 + 48 48 bits) * Basic instructions: 108 * Minimum instruction execution time: 31.3 ns ( f(CPU) = 32 MHZ / VCC1 = 4.2 to 5.5 V) 41.7 ns ( f(CPU) = 24 MHZ / VCC1 = 3.0 to 5.5 V) * Operating mode: microprocessor mode Memory ROM, RAM See Table 1.5 Product List. Power Supply Voltage Detection Vdet3 detection function, Vdet4 detection function, cold start/warm start determination function External Bus / memory expansion * Address space: 16 Mbyte Bus function * External bus interface: 1 to 7 wait states can be inserted, Expansion 4 chip select outputs, 3 V and 5 V interfaces * Bus format: Switchable between separate and multiplexed bus formats, switchable data bus width (8-bit or 16-bit) Clock Clock generation circuits * 4 circuits: Main clock, sub clock, on-chip oscillator, PLL frequency synthesizer * Oscillation stop detection: Main clock oscillation stop detection function * Frequency divider circuit: Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16 * Low power consumption features: Wait mode, stop mode Interrupts * Interrupt vectors: 70 * External interrupt inputs: NMI x 1 INT x 3 (16-bit external bus width) INT x 6 (8- bit external bus width) Key input x 4 * Interrupt priority levels: 7 Watchdog Timer 15-bit x 1 (with prescaler) DMA DMAC * 4 channels, cycle steal method * Trigger sources: 31 * Transfer modes: 2 (single transfer and repeat transfer) DMAC II * Can be activated by all peripheral function interrupt sources * Transfer modes: 2 (single transfer and burst transfer) * Immediate transfer, calculation transfer, and chain transfer functions Timer Timer A 16-bit timer x 5 Timer mode, event counter mode, one-shot timer mode, pulse width modulation (PWM) mode) Event counter 2-phase pulse signal processing (2-phase encoder input) x 3 Timer B 16-bit timer x 6 Timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode Timer function for 3-phase inverter control x 1 (using timer A1, timer A2, timer A4, 3-phase motor control and timer B2) On-chip dead time timer
Rev.1.10
Jul 15, 2007
Page 2 of 65
M32C/8A Group Table 1.2 Item Serial Interface Specifications (144-Pin Version) (2) Function UART0 to UART4 Specification Clock synchronous / asynchronous x 5 I2C bus (optional)(2), special mode 2, GCI mode, SIM mode IEBus (optional)(1)(2) 10-bit resolution x 18 channels, includes sample and hold function 8-bit resolution x 2 channels
A/D Converter D/A Converter CRC Calculation Circuit
CRC-CCITT (X16 + X12 + X5 + 1) compliant X/Y Converter 16 bits x 16 bits I/O Ports Programmable I/O ports * Input only: 1 * CMOS I/O: 81 (8-bit external bus width) 73 (16-bit external bus width) with selectable pull-up resistor * N channel open drain ports: 2 Operating Frequency / 32 MHz: VCC1 = 4.2 to 5.5 V, VCC2 = 3.0 to VCC1 24 MHz: VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 to VCC1 Supply Voltage Current Consumption 28 mA (32 MHz / VCC1 = VCC2 = 5 V) 22 mA (24 MHz / VCC1 = VCC2 = 3.3 V) 45 A (approx. 1 MHz / VCC1 = VCC2 = 3.3 V, on-chip oscillator low-power consumption mode wait mode) 0.8 A (VCC1 = VCC2 = 3.3 V, stop mode)
Operating Ambient Temperature (C) -20 to 85C, -40 to 85C (optional)(2) Package 144-pin LQFP (PLQP0144KA-A) NOTES: 1. IEBus is a registered trademark of NEC Electronics Corporation. 2. Please contact a Renesas sales office to use the optional feature.
Rev.1.10
Jul 15, 2007
Page 3 of 65
M32C/8A Group Table 1.3 Item CPU Specifications (100-Pin Version) (1) Function Central processing unit
Specification M32C/80 core (multiplier: 16 bits x 16 bits 32 bits, multiply-addition operation instructions: 16 x 16 + 48 48 bits) * Basic instructions: 108 * Minimum instruction execution time: 31.3 ns (f(CPU) = 32 MHZ / VCC1 = 4.2 to 5.5 V) 41.7 ns (f(CPU) = 24 MHZ / VCC1 = 3.0 to 5.5 V) * Operating mode: microprocessor mode Memory ROM, RAM See Table 1.5 Product List. Power Supply Voltage Detection Vdet3 detection function, Vdet4 detection function, cold start/warm start determination function External Bus / memory expansion * Address space: 16 Mbyte Bus function * External bus interface: 1 to 7 wait states can be inserted, Expansion 4 chip select outputs, 3 V and 5 V interfaces * Bus format: Switchable between separate bus and multiplexed bus formats, switchable data bus width (8-bit or 16-bit) Clock Clock generation circuits * 4 circuits: Main clock, sub clock, on-chip oscillator, PLL frequency synthesizer * Oscillation stop detection: Main clock oscillation stop detection function * Frequency divider circuit: Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16 * Low power consumption features: Wait mode, stop mode Interrupts * Interrupt vectors: 70 * External interrupt inputs: NMI x 1 INT x 3 (16-bit external bus width) INT x 6 (8- bit external bus width) Key input x 4 * Interrupt priority levels: 7 Watchdog Timer 15-bit x 1 (with prescaler) DMA DMAC * 4 channels, cycle steal method * Trigger sources: 31 * Transfer modes: 2 (single transfer and repeat transfer) DMACII * Can be activated by all peripheral function interrupt sources * Transfer modes: 2 (single transfer and burst transfer) * Immediate transfer, calculation transfer, and chain transfer functions Timer Timer A 16-bit timer x 5 Timer mode, event counter mode, one-shot timer mode, pulse width modulation (PWM) mode Event counter 2-phase pulse signal processing (2-phase encoder input) x 3 Timer B 16-bit timer x 6 Timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode Timer function for 3-phase inverter control x 1 (using timer A1, timer A2, timer A4, 3-phase motor control and timer B2) On-chip dead time timer
Rev.1.10
Jul 15, 2007
Page 4 of 65
M32C/8A Group Table 1.4 Item Serial Interface Specifications (100-Pin Version) (2) Function UART0 to UART4 Specification Clock synchronous / asynchronous x 5 I2C bus (optional)(2), special mode 2, GCI mode, SIM mode IEBus (optional)(1)(2) 10-bit resolution x 10 channels, includes sample and hold function 8-bit resolution x 2 channels
A/D Converter D/A Converter CRC Calculation Circuit
CRC-CCITT (X16 + X12 + X5 + 1) compliant X/Y Converter 16 bits x 16 bits I/O Ports Programmable I/O ports * Input only: 1 * CMOS I/O: 45 (8-bit external bus width) 37 (16-bit external bus width) with selectable pull-up resistor * N channel open drain ports: 2 Operating Frequency / 32 MHz: VCC1 = 4.2 to 5.5 V, VCC2 = 3.0 to VCC1 24 MHz: VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 to VCC1 Supply Voltage Current Consumption 28 mA (32 MHz / VCC1 = VCC2 = 5 V) 22 mA (24 MHz / VCC1 = VCC2 = 3.3 V) 45 A (approx. 1 MHz / VCC1 = VCC2 = 3.3 V, on-chip oscillator low-power consumption mode wait mode) 0.8 A (VCC1 = VCC2 = 3.3 V, stop mode)
Operating Ambient Temperature (C) -20 to 85C, -40 to 85C (optional)(2) Package 100-pin LQFP (PLQP0100KB-A) NOTES: 1. IEBus is a registered trademark of NEC Electronics Corporation. 2. Please contact a Renesas sales office for optional features.
Rev.1.10
Jul 15, 2007
Page 5 of 65
M32C/8A Group
1.2
Product List
Table 1.5 lists product information. Figure 1.1 shows product numbering system. Table 1.5 Product List (M32C/8A)
Package PLQP0100KB-A (100P6Q-A) (P) PLQP0100KB-A (100P6Q-A) (P) PLQP0144KA-A (144P6Q-A) ROM Capacity -
Current as of July. 2007
RAM Capacity 12KB 24KB 24KB Remarks ROMless ROMless ROMless
Type No. M308A0SGP M308A3SGP M308A5SGP
(P): Under planning
Part No.
M30 8A x S GP
Package type option GP: Package PLQP0100KB-A (100P6Q-A) Package PLQP0144KA-A (144P6Q-A) Memory type S: ROMless version Shows RAM capacity, pin count, etc. (The value itself has no specific meaning) M32C/8A Group M16C Family
Figure 1.1
Product Numbering System
Rev.1.10
Jul 15, 2007
Page 6 of 65
M32C/8A Group
1.3
Block Diagram
Figure 1.2 shows a M32C/8A Group block diagram.
8
(2)
8
(2)
8
(2)
8
(2)
8
(2)
8
(2)
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7

Internal peripheral functions
Timers (16-bit) Output (timer A): 5 Input (timer B): 6 Three-phase motor control circuit 10-bit A/D converter: 1 circuit, 18 input (3) 8-bit D/A converters: 2 circuits DMAC: 4 channels Clock generation circuits: XIN-XOUT XCIN-XCOUT On-chip oscillator PLL frequency synthesizer DMAC II
Watchdog timer (15 bits)
M32C/80 Series CPU core
Serial Interface: 5 channels clock synchronous/ asynchronous CRC calculation circuit X16 + X12 + X5 + 1 (CCITT) X/Y converter: 16 bits x 16 bits R0H R1H R2 R3 A0 A1 FB SB SVP VCT R0L R1L INTB ISP USP PC SVF FLG
Memory
RAM
Multiplier
(1)

(1)
(1)
(1)
(1)

Port P10 Port P9 P8_5 Port P8
Port P13
Port P12
Port P11
Port P15
Port P14
8
8
5
8
7
8
8
7
NOTES: 1. Ports P11 to P15 are provided in the 144-pin package only. 2. Ports P0 to P5 function as bus control pins when using in microprocessor mode . Port P1 can function as I/O port when using with 8-bit external bus width only. 3. 18 channels are available in the 144-pin package. 10 channels are available in the 100-pin package.
Figure 1.2
M32C/8A Group Block Diagram
Rev.1.10
Jul 15, 2007
Page 7 of 65
M32C/8A Group
1.4
Pin Assignments
Figures 1.3 and 1.4 show a pin assignment (top view).
( note 3 )
D9 D10 D11 D12 INT3 / D13 INT4 / D14 INT5 / D15 A0 , [ A0 / D0 A1 , [ A1 / D1 A2 , [ A2 / D2 A3 , [ A3 / D3 A4 , [ A4 / D4 A5 , [ A5 / D5 A6 , [ A6 / D6 A7 , [ A7 / D7
A8 , [ A8 / D8 ]
A9 , [ A9 / D9 ] A10 , [ A10 / D10 A11 , [ A11 / D11 A12 , [ A12 / D12 A13 , [ A13 / D13 A14 , [ A14 / D14 A15 , [ A15 / D15 A16 A17
] ] ] ] ] ] ] ]
] ] ] ] ] ]
A18
76 75 74
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
73
P1_1 / P1_2 / P1_3 / P1_4 / P1_5 / P1_6 / P1_7 / P2_0 / P2_1 / P2_2 / P2_3 / P2_4 / P2_5 / P2_6 / P2_7 / VSS P3_0 / VCC2 P12_0 P12_1 P12_2 P12_3 P12_4 P3_1 / P3_2 / P3_3 / P3_4 / P3_5 / P3_6 / P3_7 / P4_0 / P4_1 / VSS P4_2 / VCC2 P4_3 /
A19
D8 / P1_0 D7 / P0_7 D6 / P0_6 D5 / P0_5 D4 / P0_4 P11_4 P11_3 P11_2 P11_1 P11_0 D3 / P0_3 D2 / P0_2 D1 / P0_1 D0 / P0_0 AN15_7 / P15_7 AN15_6 / P15_6 AN15_5 / P15_5 AN15_4 / P15_4 AN15_3 / P15_3 AN15_2 / P15_2 AN15_1 / P15_1 VSS AN15_0 / P15_0 VCC1 AN_7 / KI3 / P10_7 AN_6 / KI2 / P10_6 AN_5 / KI1 / P10_5 AN_4 / KI0 / P10_4 AN_3 / P10_3 AN_2 / P10_2 AN_1 / P10_1 AVSS AN_0 / P10_0 VREF AVCC ADTRG / STXD4 / SCL4 / RXD4 / P9_7
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144

M32C/8A Group PLQP0144KA-A (144P6Q-A) (top view)

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
P4_4 / CS3 / A20 P4_5 / CS2 / A21 P4_6 / CS1 / A22 P4_7 / CS0 / A23 P12_5 P12_6 P12_7 P5_0 / WRL / WR P5_1 / WRH / BHE P5_2 / RD P5_3 / CLKOUT / BCLK / ALE P13_0 P13_1 VCC2 P13_2 VSS P13_3 P5_4 / HLDA / ALE P5_5 / HOLD P5_6 / ALE P5_7 / RDY P13_4 P13_5 P13_6 P13_7 P6_0 / CTS0 / RTS0 / SS0 P6_1 / CLK0 P6_2 / RXD0 / SCL0 / STXD0 P6_3 / TXD0 / SDA0 / SRXD0 P6_4 / CTS1 / RTS1 / SS1 P6_5 / CLK1 VSS P6_6 / RXD1 / SCL1 / STXD1 VCC1 P6_7 / TXD1 / SDA1 / SRXD1 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 (1)
1
2
3
4
5
6
7
8
( note 2 )
Figure 1.3
Pin Assignment for 144-pin Package
Rev.1.10
Jul 15, 2007
Page 8 of 65
/ P9_6 / P9_5 / P9_4 / P9_3 / P9_2 / P9_1 / P9_0 P14_6 P14_5 P14_4 P14_3 P14_2 P14_1 P14_0 BYTE CNVSS XCIN / P8_7 XCOUT / P8_6 RESET XOUT VSS XIN VCC1 NMI / P8_5 INT2 / P8_4 INT1 / P8_3 INT0 / P8_2 U / TA4IN / P8_1 U / TA4OUT / P8_0 TA3IN / P7_7 TA3OUT / P7_6 W / TA2IN / P7_5 W / TA2OUT / P7_4 SS2 / RTS2 / CTS2 / V / TA1IN / P7_3 CLK2 / V / TA1OUT / P7_2 (1) STXD2 / SCL2 / RXD2 / TB5IN / TA0IN / P7_1 ANEX1 / TXD4 / SDA4 / SRXD4 ANEX0 / CLK4 DA1 / SS4 / RTS4 / CTS4 / TB4IN DA0 / SS3 / RTS3 / CTS3 / TB3IN SRXD3 / SDA3 / TXD3 / TB2IN STXD3 / SCL3 / RXD3 / TB1IN CLK3 / TB0IN
NOTES: 1. P7_0 and P7_1 are N-channel open drain output. 2. Confirm the pin 1 position on the package by referring to Package Dimensions. 3. Pin names in square brackets [ ] correspond to signal function names.
9
M32C/8A Group Table 1.6
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCC1 P6_6 VSS P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P13_7 P13_6 P13_5 CLK1 CTS1/RTS1/SS1 TXD0/SDA0/SRXD0 RXD0/SCL0/STXD0 CLK0 CTS0/RTS0/SS0 RXD1/SCL1/STXD1
144-Pin Version List of Pin Names (1)
Port
P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 P14_6 P14_5 P14_4 P14_3 P14_2 P14_1 P14_0
Control Pin
Interrupt Pin
Timer Pin
UART Pin
TXD4/SDA4/SRXD4 CLK4
Analog Pin
ANEX1 ANEX0 DA1 DA0
Bus Control Pin
TB4IN TB3IN TB2IN TB1IN TB0IN
CTS4/RTS4/SS4 CTS3/RTS3/SS3 TXD3/SDA3/SRXD3 RXD3/SCL3/STXD3 CLK3
BYTE CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC1
P8_7 P8_6
P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7
NMI INT2 INT1 INT0 TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA0IN/TB5IN TA0OUT CTS2/RTS2/SS2 CLK2 RXD2/SCL2/STXD2 TXD2/SDA2/SRXD2 TXD1/SDA1/SRXD1
Rev.1.10
Jul 15, 2007
Page 9 of 65
M32C/8A Group Table 1.7
Pin No.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VCC2 P4_2 VSS P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P12_4 P12_3 P12_2 P12_1 P12_0 VCC2 P3_0 VSS P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 A7,[A7/D7] A6,[A6/D6] A5,[A5/D5] A4,[A4/D4] A3,[A3/D3] A2,[A2/D2] A1,[A1/D1] A8,[A8/D8] A17 A16 A15,[A15/D15] A14,[A14/D14] A13,[A13/D13] A12,[A12/D12] A11,[A11/D11] A10,[A10/D10] A9,[A9/D9] A18 VSS P13_2 VCC2 P13_1 P13_0 P5_3 P5_2 P5_1 P5_0 P12_7 P12_6 P12_5 P4_7 P4_6 P4_5 P4_4 P4_3
144-Pin Version List of Pin Names (2)
Port
P13_4 P5_7 P5_6 P5_5 P5_4 P13_3
Control Pin
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
RDY ALE HOLD HLDA/ALE
CLKOUT
BCLK/ALE RD WRH/BHE WRL/WR
CS0/A23 CS1/A22 CS2/A21 CS3/A20 A19
Rev.1.10
Jul 15, 2007
Page 10 of 65
M32C/8A Group Table 1.8
Pin No.
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 VSS 131 132 VCC1 133 134 135 136 137 138 139 140 AVSS 141 142 VREF 143 AVCC 144
144-Pin Version List of Pin Names (3)
Port
P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P11_4 P11_3 P11_2 P11_1 P11_0 P0_3 P0_2 P0_1 P0_0 P15_7 P15_6 P15_5 P15_4 P15_3 P15_2 P15_1 P15_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 P10_0 KI3 KI2 KI1 KI0
Control Pin
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
A0,[A0/D0] D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
INT5 INT4 INT3
D3 D2 D1 D0 AN15_7 AN15_6 AN15_5 AN15_4 AN15_3 AN15_2 AN15_1 AN15_0 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1 AN_0
P9_7
RXD4/SCL4/STXD4
ADTRG
Rev.1.10
Jul 15, 2007
Page 11 of 65
M32C/8A Group
(note 3)
D11 D12 INT3 / D13 INT4 / D14 INT5 / D15 A0 , [ A0 / D0 ] A1 , [ A1 / D1 ]
A8 , [ A8 / D8 ]
[ [ [ [ [ [
A2 A3 A4 A5 A6 A7
, , , , , ,
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P1_3 / P1_4 / P1_5 / P1_6 / P1_7 / P2_0 / P2_1 / P2_2 / P2_3 / P2_4 / P2_5 / P2_6 / P2_7 / VSS P3_0 / VCC2 P3_1 / P3_2 / P3_3 / P3_4 / P3_5 / P3_6 / P3_7 / P4_0 / P4_1 /
A2 A3 A4 A5 A6 A7
A9 , A10 A11 A12 A13 A14 A15 A16 A17
[ , , , , , ,
A9 / D9 ] [ A10 / D10 [ A11 / D11 [ A12 / D12 [ A13 / D13 [ A14 / D14 [ A15 / D15
/ / / / / /
D2 D3 D4 D5 D6 D7
] ] ] ] ] ]
] ] ] ] ] ]
D10 / P1_2 D9 / P1_1 D8 / P1_0 D7 / P0_7 D6 / P0_6 D5 / P0_5 D4 / P0_4 D3 / P0_3 D2 / P0_2 D1 / P0_1 D0 / P0_0 AN_7 / KI3 / P10_7 AN_6 / KI2 / P10_6 AN_5 / KI1 / P10_5 AN_4 / KI0 / P10_4 AN_3 / P10_3 AN_2 / P10_2 AN_1 / P10_1 AVSS AN_0 / P10_0 VREF AVCC ADTRG / STXD4 / SCL4 / RXD4 / P9_7 ANEX1 / SRXD4 / SDA4 / TXD4 / P9_6 ANEX0 / CLK4 / P9_5
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50

49 48 47 46 45 44 43
M32C/8A Group PLQP0100KB-A (100P6Q-A) (top view)
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
P4_2 / A18 P4_3 / A19 P4_4 / CS3 / A20 P4_5 / CS2 / A21 P4_6 / CS1 / A22 P4_7 / CS0 / A23 P5_0 / WRL / WR P5_1 / WRH / BHE P5_2 / RD P5_3 / CLKOUT / BCLK / ALE P5_4 / HLDA / ALE P5_5 / HOLD P5_6 / ALE P5_7 / RDY P6_0 / CTS0 / RTS0 / SS0 P6_1 / CLK0 P6_2 / RXD0 / SCL0 / STXD0 P6_3 / TXD0 / SDA0 / SRXD0 P6_4 / CTS1 / RTS1 / SS1 P6_5 / CLK1 P6_6 / RXD1 / SCL1 / STXD1 P6_7 / TXD1 / SDA1 / SRXD1 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2(1) P7_1 / TA0IN / TB5IN / RXD2 / SCL2 / STXD2(1) P7_2 / TA1OUT / V / CLK2

27 26
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P9_4 P9_3 P9_2 P9_1 P9_0 BYTE CNVSS XCIN / P8_7 XCOUT / P8_6 RESET XOUT
/ / / / /
DA1 / SS4 / RTS4 / CTS4 DA0 / SS3 / RTS3 / CTS3 SRXD3 / SDA3 / TXD3 STXD3 / SCL3 / RXD3 CLK3
NOTES: 1. P7_0 and P7_1 are N-channel open drain output. 2. Confirm the pin 1 position on the package by referring to Package Dimensions. 3. Pin names in square brackets [ ] correspond to signal function names.
Figure 1.4
Pin Assignment for 100-pin Package
Rev.1.10
Jul 15, 2007
Page 12 of 65
NMI INT2 INT1 INT0 U / TA4IN U / TA4OUT TA3IN TA3OUT W / TA2IN W / TA2OUT SS2 / RTS2 / CTS2 / V / TA1IN
/ / / / /
TB4IN TB3IN TB2IN TB1IN TB0IN
VSS XIN VCC1 / P8_5 / P8_4 / P8_3 / P8_2 / P8_1 / P8_0 / P7_7 / P7_6 / P7_5 / P7_4 / P7_3
25
1
2
3
4
5
6
7
8
9
(note 2)
M32C/8A Group Table 1.9
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CLKOUT
100-Pin Version List of Pin Names (1)
Port
P9_4 P9_3 P9_2 P9_1 P9_0
Control Pin
Interrupt Pin
Timer Pin
TB4IN TB3IN TB2IN TB1IN TB0IN
UART Pin
CTS4/RTS4/SS4 CTS3/RTS3/SS3 TXD3/SDA3/SRXD3 RXD3/SCL3/STXD3 CLK3
Analog Pin
DA1 DA0
Bus Control Pin
BYTE CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC1
P8_7 P8_6
P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6 P5_5 P5_4 P5_3 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 P4_3 P4_2
NMI INT2 INT1 INT0 TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA0IN/TB5IN TA0OUT CTS2/RTS2/SS2 CLK2 RXD2/SCL2/STXD2 TXD2/SDA2/SRXD2 TXD1/SDA1/SRXD1 RXD1/SCL1/STXD1 CLK1 CTS1/RTS1/SS1 TXD0/SDA0/SRXD0 RXD0/SCL0/STXD0 CLK0 CTS0/RTS0/SS0 RDY ALE HOLD HLDA/ALE BCLK/ALE RD WRH/BHE WRL/WR CS0/A23 CS1/A22 CS2/A21 CS3/A20 A19 A18
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M32C/8A Group Table 1.10
Pin No.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
100-Pin Version List of Pin Names (2)
Port
P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1
Control Pin
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
A17 A16 A15,[A15/D15] A14,[A14/D14] A13,[A13/D13] A12,[A12/D12] A11,[A11/D11] A10,[A10/D10] A9,[A9/D9] A8,[A8/D8] A7,[A7/D7] A6,[A6/D6] A5,[A5/D5] A4,[A4/D4] A3,[A3/D3] A2,[A2/D2] A1,[A1/D1] A0,[A0/D0] D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VCC2 P3_0 VSS P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 AVSS P10_0 VREF AVCC P9_7 P9_6 P9_5 RXD4/SCL4/STXD4 TXD4/SDA4/SRXD4 CLK4 ADTRG ANEX1 ANEX0 AN_0
INT5 INT4 INT3
KI3 KI2 KI1 KI0
AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1
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M32C/8A Group
1.5
Pin Functions
Pin Functions (1) (100-Pin Package and 144-Pin Package)
Pin Name VCC1,VCC2 VSS AVCC AVSS RESET CNVSS BYTE I/O Supply Description Type Voltage - - Apply 3.0 to 5.5 V to pins VCC1 and VCC2, and 0 V to the VSS pin. The input condition of VCC1 VCC2 must be met. - VCC1 Power supply input pins to the A/D converter and D/A converter. Connect the AVCC pin to VCC1, and the AVSS pin to VSS. I VCC1 The MCU is placed in a reset state when applying an "L" signal to the RESET pin. I VCC1 This pin switches processor mode. Apply an "H" signal to the CNVSS pin to start up in microprocessor mode. I VCC1 This pin switches data bus width in external memory space 3. A data bus is 16 bits wide when the BYTE pin is held "L" and 8 bits wide when it is held "H". I/O VCC2 Data (D0 to D7) input/output pins while accessing an external memory space with separate bus. I/O VCC2 Data (D8 to D15) inputs/output pins while accessing an external memory space with 16-bit separate bus. O VCC2 Address bits (A0 to A22) output pins. O VCC2 Inverted address bit (A23) output pin. I/O VCC2 Data (D0 to D7) input/output and 8 low-order address bits (A0 to A7) output are performed by time-sharing these pins while accessing an external memory space with multiplexed bus. Data (D8 to D15) input/output and 8 middle-order address bits (A8 to A15) output are performed by time-sharing these pins while accessing an external memory space with 16-bit multiplexed bus. Chip-select signal output pins used to specify external devices. WRL, WRH, (WR, BHE) and RD signal output pins. WRL and WRH can be switched with WR and BHE by program. * WRL, WRH and RD are selected: If external data bus is 16 bits wide, data is written to an even address in external memory space while an "L" is output from the WRL pin. Data is written to an odd address while an "L" is output from the WRH pin. Data is read while an "L" is output from the RD pin. * WR, BHE and RD are selected: Data is written while an "L" is output from the WR pin. Data is read while an "L" is output from the RD pin. Data in odd address is accessed while an "L" is output from the BHE pin. Select WR, BHE and RD when an external data bus is 8 bits wide. ALE signal is used for the external devices to latch address signals when the multiplexed bus is selected. The MCU is placed in a hold state while an "L" signal is applied to the HOLD pin. The HLDA pin outputs an "L" while the MCU is placed in a hold state Bus is placed in a wait state while an "L" signal is applied to the RDY pin.
Table 1.11
Item Power supply Analog power supply input Reset input CNVSS External data bus width select input Bus control Pins
D0 to D7 D8 to D15 A0 to A22 A23 A0/D0 to A7/D7 A8/D8 to A15/D15 CS0 to CS3 WRL/WR WRH/BHE RD
I/O
VCC2
O O
VCC2 VCC2
ALE HOLD HLDA RDY
O I O I
VCC2 VCC2 VCC2 VCC2
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M32C/8A Group Table 1.12
Item Main clock input Main clock output Sub clock input Sub clock output BCLK output Clock output INT interrupt input NMI interrupt input Timer A
Pin Functions (2) (100-Pin Package and 144-Pin Package)
Pin Name XIN XOUT XCIN XCOUT BCLK CLKOUT INT0 to INT2 NT3 to INT5 NMI TA0OUT to TA4OUT TA0IN to TA4IN TB0IN to TB5IN U, U, V, V, W, W CTS0 to CTS4 RTS0 to RTS4 CLK0 to CLK4 RXD0 to RXD4 TXD0 to TXD4 SDA0 to SDA4 SCL0 to SCL4 I/O Supply Description Type Voltage I VCC1 Input/output pins for the main clock oscillation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. To O VCC1 apply an external clock, apply it to XIN and leave XOUT open I O O O I I I I/O I I O VCC1 VCC1 VCC2 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 NMI interrupt input pin. Connect the NMI pin to VCC1 via a resistor when the NMI interrupt is not used. Timer A0 to A4 input/output pins (TA0OUT is N-channel open drain output) Timer A0 to A4 input pins Timer B0 to B5 input pins Three-phase motor control timer output pins Input/output pins for the sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT. To apply an external clock, apply it to XCIN and leave XCOUT open. Bus clock output pin The CLKOUT pin outputs the clock having the same frequency as fC, f8, or f32 INT interrupt input pins
Timer B Three-phase motor control timer output Serial interface
I O I/O I O I/O I/O O I I
VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1
Input pins to control data transmission Output pins to control data reception Serial clock input/output pins Serial data input pins Serial data output pins (TXD2 is N-channel open drain output) Serial data input/output pins (SDA2 is N-channel open drain output) Serial clock input/output pins (SCL2 is N-channel open drain output) Serial data output pins when slave mode is selected (STXD2 is N-channel open drain output) Serial data input pins when slave mode is selected Control input pins used in the serial interface special mode.
I2C mode
STXD0 to Serial STXD4 interface special function SRXD0 to SRXD4 SS0 to SS4
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M32C/8A Group Table 1.13
Item Reference voltage input A/D converter
Pin Functions (3) (100-Pin Package and 144-Pin Package)
Pin Name VREF AN_0 to AN_7 ADTRG ANEX0 I/O Supply Type Voltage I - I I I/O VCC1 VCC1 VCC1 VCC1 VCC1 VCC2 Description The VREF pin supplies the reference voltage to the A/D converter and D/A converter. Analog input pins for the A/D converter. External trigger input pin for the A/D converter. Extended analog input pin for the A/D converter or output pin in external op-amp connection mode. Extended analog input pin for the A/D converter. Output pins for the D/A converter. 8-bit CMOS I/O ports. The Port Pi Direction Register determines if each pin is used as an input port or an output port. The Pull-up Control Register determines if the input ports, divided into groups of four, are pulled up or not.
D/A converter I/O port
Input port Key input interrupt input
ANEX1 I DA0, DA1 O P0_0 to P0_7, I/O(1) P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 P6_0 to P6_7, I/O P7_0 to P7_7, P9_0 to P9_7, P10_0 to P10_7 P8_0 to P8_4 P8_6, P8_7 P8_5 I KI0 to KI3 I
VCC1
These 8-bit I/O ports are functionally equivalent to P0. (P7_0 and P7_1 are N-channel open drain output.)
These I/O ports are functionally equivalent to P0. VCC1 VCC1 Shares the pin with NMI. Input port to read NMI pin level. Key input interrupt input pins
NOTE: 1. P0 to P5 function as bus control pins and cannot be used as I/O ports. P1_0 to P1_7 can be used as I/O ports when using with 8-bit external bus width only.
Table 1.14
Item A/D converter I/O ports
Pin Functions (4) (144-Pin Package Only)
Pin Name AN15_0 to AN15_7 P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7 P14_0 to P14_6, P15_0 to P15_7 I/O Supply Description Type Voltage I VCC1 Analog input pins for the A/D converter I/O VCC2 These I/O ports are functionally equivalent to P0.
I/O
VCC1
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M32C/8A Group
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The register bank is comprised of eight registers (R0, R1, R2, R3, A0, A1, SB, and FB) out of 28 CPU registers. There are two sets of register banks.
b31
b15
b0
General registers
R2 R2 R3 R3
b23
R0H R0H R1H R1H R2 R2 R3 R3 A0 A0 A1 A1 SB SB FB FB USP ISP INTB PC FLG
b15 b8 b7
R0L R0L R1L R1L
Data registers(1)
Address registers(1) Static base register(1) Frame base register(1) User stack pointer Interrupt stack pointer Interrupt table register Program counter Flag register
b0
IPL
U I OBSZDC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved Processor interrupt priority level Reserved
b15 b0
High-speed interrupt registers
b23
SVF SVP VCT
b7 b0
Flag save register PC save register Vector register
DMAC-associated registers
b15
DMD0 DMD1 DCT0 DCT1 DRC0 DRC1 DMA0 DMA1 DRA0 DRA1 DSA0 DSA1
DMA mode registers DMA transfer count registers DMA transfer count reload registers DMA memory address registers DMA memory address reload registers DMA SFR address registers
b23
NOTE: 1. These registers comprise a register bank. There are two sets of register banks (register bank 0 and register bank 1).
Figure 2.1
CPU Register
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M32C/8A Group
2.1 2.1.1
General Registers Data Registers (R0, R1, R2, and R3)
R0, R1, R2, and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order (R0H/R1H) and low-order bits (R0L/R1L) to be used separately as 8-bit data registers. R0 can be combined with R2 and used as a 32-bit data register (R2R0). The same applies to R3R1.
2.1.2
Address Registers (A0 and A1)
A0 and A1 are 24-bit registers used for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arithmetic and logic operations.
2.1.3
Static Base Register (SB)
SB is a 24-bit register used for SB-relative addressing.
2.1.4
Frame Base Register (FB)
FB is a 24-bit register used for FB-relative addressing.
2.1.5
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently.
2.1.6
Interrupt Table Register (INTB)
INTB is a 24-bit register indicating the starting address of a relocatable interrupt vector table.
2.1.7
Program Counter (PC)
PC is 24 bits wide and indicates the address of the next instruction to be executed.
2.1.8
Flag Register (FLG)
FLG is a 16-bit register indicating the CPU state.
2.1.8.1
Carry Flag (C)
The C flag indicates whether or not carry or borrow has been generated after executing an instruction.
2.1.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.1.8.3
Zero Flag (Z)
The Z flag becomes 1 when an arithmetic operation results in 0; otherwise becomes 0.
2.1.8.4
Sign Flag (S)
The S flag becomes 1 when an arithmetic operation results in a negative value; otherwise becomes 0.
2.1.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is set to 0. Register bank 1 is selected when this flag is set to 1.
2.1.8.6
Overflow Flag (O)
The O flag becomes 1 when an arithmetic operation results in an overflow; otherwise becomes 0.
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M32C/8A Group
2.1.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0 and enabled when it is set to 1. The I flag becomes 0 when an interrupt request is acknowledged.
2.1.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0. USP is selected when the U flag is set to 1. The U flag becomes 0 when a hardware interrupt request is acknowledged or the INT instruction specifying software interrupt numbers 0 to 31 is executed.
2.1.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.1.8.10 Reserved Space
Only write 0 to bits assigned to the reserved space. When read, the bits return undefined values.
2.2
High-Speed Interrupt Registers
Registers associated with the high-speed interrupt are follows: * Save flag register (SVF) * Save PC register (SVP) * Vector register (VCT)
2.3
DMAC-Associated Registers
Registers associated with the DMAC are as follows: * DMA mode register (DMD0, DMD1) * DMA transfer count register (DCT0, DCT1) * DMA transfer count reload register (DRC0, DRC1) * DMA memory address register (DMA0, DMA1) * DMA memory address reload register (DRA0, DRA1) * DMA SFR address register (DSA0, DSA1)
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M32C/8A Group
3.
Memory
Figure 3.1 is a memory map of the M32C/8A Group. The M32C/8A Group has 16-Mbyte address space from addresses 000000h to FFFFFFh. The fixed interrupt vectors are allocated addresses FFFFDCh to FFFFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses, beginning with address 000400h. For example, a 12-Kbyte internal RAM area is allocated addresses 000400h to 0033FFh. The internal RAM is used not only for storing data but for the stacks when subroutines are called or when interrupt requests are acknowledged. SFRs are allocated address 000000h to 0003FFh. The peripheral function control registers such as for I/O ports, A/D converters, serial interfaces, timers are allocated here. All blank spaces within SFRs are reserved and cannot be accessed by users. The special page vectors are allocated addresses FFFE00h to FFFFDBh. They are used for the JMPS instruction and JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details.
000000h SFR 000400h Internal RAM XXXXXXh 010000h Reserved FFFE00h FFFFDCh
Special page vector table Undefined instruction Overflow BRK instruction Address match
External Space Watchdog timer (1) NMI FFFFFFh FFFFFFh Reset
Internal RAM Capacity 12 Kbytes 24 Kbytes XXXXXXh 0033FFh 0063FFh
NOTE: 1. The watchdog timer interrupt, oscillation stop detection interrupt , and Vdet4 detection interrupt use the same vector.
Figure 3.1
Memory Map
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M32C/8A Group
4.
Special Function Registers (SFRs)
Special Function Registers (SFRs) are the control registers of peripheral functions. Tables 4.1 to 4.11 list SFR address maps. Table 4.1
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh Vdet4 Detection Interrupt Register D4INT XX00 0000b Address Match Interrupt Register 5 RMAD5 000000h Address Match Interrupt Register 4 RMAD4 000000h PLL Control Register 0 PLL Control Register 1 PLC0 PLC1 0001 X010b 000X 0000b Address Match Interrupt Register 3 RMAD3 000000h Voltage Detection Register 1 VCR1 0000 1000b Address Match Interrupt Register 2 RMAD2 000000h Voltage Detection Register 2 VCR2 00h Address Match Interrupt Register 1 RMAD1 000000h Processor Mode Register 2 PM2 00h Address Match Interrupt Register 0 RMAD0 000000h Address Match Interrupt Enable Register Protect Register External Data Bus Width Control Register Main Clock Division Register Oscillation Stop Detection Register Watchdog Timer Start Register Watchdog Timer Control Register AIER PRCR DS MCD CM2 WDTS WDC 00h XXXX 0000b XXXX 1000b(BYTE="L") XXXX 0000b(BYTE="H") XXX0 1000b 00h XXh 00XX XXXXb Processor Mode Register 0(1) Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1
0000 0011b(CNVSS="H")
SFR Address Map (1)
Register Symbol After Reset
00h 0000 1000b 0010 0000b
X: Undefined Blank spaces are all reserved. No access is allowed. NOTE: 1. Bits PM01 and PM00 in the PM0 register maintain values set before reset, even after software reset or watchdog timer reset has been performed.
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M32C/8A Group Table 4.2
Address 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh X: Undefined Blank spaces are all reserved. No access is allowed. External Space Wait Control Register 0 External Space Wait Control Register 1 External Space Wait Control Register 2 External Space Wait Control Register 3 Page Mode Wait Control Register 0 Page Mode Wait Control Register 1 EWCR0 EWCR1 EWCR2 EWCR3 PWCR0 PWCR1 X0X0 0011b X0X0 0011b X0X0 0011b X0X0 0011b 0001 0001b 0001 0001b Address Match Interrupt Register 7 RMAD7 000000h Address Match Interrupt Register 6 RMAD6 000000h
SFR Address Map (2)
Register Symbol After Reset
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M32C/8A Group Table 4.3
Address 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh DMA1 Interrupt Control Register UART2 Transmit/NACK Interrupt Control Register DMA3 Interrupt Control Register UART3 Transmit/NACK Interrupt Control Register Timer A1 Interrupt Control Register UART4 Transmit/NACK Interrupt Control Register Timer A3 Interrupt Control Register UART2 Bus Conflict Detection Interrupt Control Register DM1IC S2TIC DM3IC S3TIC TA1IC S4TIC TA3IC BCN2IC XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b INT1 Interrupt Control Register INT1IC XX00 X000b INT3 Interrupt Control Register INT3IC XX00 X000b INT5 Interrupt Control Register INT5IC XX00 X000b Timer B3 Interrupt Control Register TB3IC XXXX X000b Timer B1 Interrupt Control Register TB1IC XXXX X000b DMA0 Interrupt Control Register Timer B5 Interrupt Control Register DMA2 Interrupt Control Register UART2 Receive/ACK Interrupt Control Register Timer A0 Interrupt Control Register UART3 Receive/ACK Interrupt Control Register Timer A2 Interrupt Control Register UART4 Receive/ACK Interrupt Control Register Timer A4 Interrupt Control Register UART0/UART3 Bus Conflict Detection Interrupt Control Register UART0 Receive/ACK Interrupt Control Register A/D0 Conversion Interrupt Control Register UART1 Receive/ACK Interrupt Control Register DM0IC TB5IC DM2IC S2RIC TA0IC S3RIC TA2IC S4RIC TA4IC BCN0IC/BCN3IC S0RIC AD0IC S1RIC XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b
SFR Address Map (3)
Register Symbol After Reset
X: Undefined Blank spaces are all reserved. No access is allowed.
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M32C/8A Group Table 4.4
Address 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh to 02BFh X: Undefined Blank spaces are all reserved. No access is allowed. INT0 Interrupt Control Register Exit Priority Register INT0IC RLVL XX00 X000b XXXX 0000b INT2 Interrupt Control Register INT2IC XX00 X000b INT4 Interrupt Control Register INT4IC XX00 X000b Timer B4 Interrupt Control Register TB4IC XXXX X000b Timer B2 Interrupt Control Register TB2IC XXXX X000b
SFR Address Map (4)
Register UART0 Transmit/NACK Interrupt Control Register UART1/UART4 Bus Conflict Detection Interrupt Control Register UART1 Transmit/NACK Interrupt Control Register Key Input Interrupt Control Register Timer B0 Interrupt Control Register S0TIC BCN1IC/BCN4IC S1TIC KUPIC TB0IC Symbol After Reset XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b
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M32C/8A Group Table 4.5
Address 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh 02E0h 02E1h 02E2h 02E3h 02E4h 02E5h 02E6h 02E7h 02E8h 02E9h 02EAh 02EBh 02ECh 02EDh 02EEh 02EFh UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART1 Transmit/Receive Mode Register UART1 Baud Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB 00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh X0 Register, Y0 Register X1 Register, Y1 Register X2 Register, Y2 Register X3 Register, Y3 Register X4 Register, Y4 Register X5 Register, Y5 Register X6 Register, Y6 Register X7 Register, Y7 Register X8 Register, Y8 Register X9 Register, Y9 Register X10 Register, Y10 Register X11 Register, Y11 Register X12 Register, Y12 Register X13 Register, Y13 Register X14 Register, Y14 Register X15 Register, Y15 Register X/Y Control Register
SFR Address Map (5)
Register Symbol
X0R, Y0R XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh
After Reset
X1R, Y1R X2R, Y2R X3R, Y3R X4R, Y4R X5R, Y5R X6R, Y6R X7R, Y7R X8R, Y8R X9R, Y9R X10R, Y10R X11R, Y11R X12R, Y12R X13R, Y13R X14R, Y14R X15R, Y15R XYC
XXXX XX00b
X: Undefined Blank spaces are all reserved. No access is allowed.
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M32C/8A Group Table 4.6
Address 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh 0310h 0311h 0312h 0313h 0314h 0315h 0316h 0317h 0318h 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh External Interrupt Source Select Register IFSR 00h Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register TB3MR TB4MR TB5MR 00XX 0000b 00XX 0000b 00XX 0000b Timer B3 Register Timer B4 Register Timer B5 Register TB3 TB4 TB5 XXXXh XXXXh XXXXh Timer A11 Register Timer A21 Register Timer A41 Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 XXXXh XXXXh XXXXh 00h 00h XX11 1111b XX11 1111b XXh XXh UART4 Special Mode Register 4 UART4 Special Mode Register 3 UART4 Special Mode Register 2 UART4 Special Mode Register UART4 Transmit/Receive Mode Register UART4 Baud Rate Register UART4 Transmit Buffer Register UART4 Transmit/Receive Control Register 0 UART4 Transmit/Receive Control Register 1 UART4 Receive Buffer Register Timer B3, B4, B5 Count Start Register U4SMR4 U4SMR3 U4SMR2 U4SMR U4MR U4BRG U4TB U4C0 U4C1 U4RB TBSR 00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 000X XXXXb
SFR Address Map (6)
Register Symbol After Reset
X: Undefined Blank spaces are all reserved. No access is allowed.
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M32C/8A Group Table 4.7
Address 0320h 0321h 0322h 0323h 0324h 0325h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 044Ch 034Dh 034Eh 034Fh Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register TA0 TA1 TA2 TA3 TA4 XXXXh XXXXh XXXXh XXXXh XXXXh UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Baud Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register Count Start Register Clock Prescaler Reset Register One-Shot Start Register Trigger Select Register Up/Down Select Register U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB TABSR CPSRF ONSF TRGSR UDF 00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 00h 0XXX XXXXb 00h 00h 00h UART3 Special Mode Register 4 UART3 Special Mode Register 3 UART3 Special Mode Register 2 UART3 Special Mode Register UART3 Transmit/Receive Mode Register UART3 Baud Rate Register UART3 Transmit Buffer Register UART3 Transmit/Receive Control Register 0 UART3 Transmit/Receive Control Register 1 UART3 Receive Buffer Register U3SMR4 U3SMR3 U3SMR2 U3SMR U3MR U3BRG U3TB U3C0 U3C1 U3RB 00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
SFR Address Map (7)
Register Symbol After Reset
X: Undefined Blank spaces are all reserved. No access is allowed.
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M32C/8A Group Table 4.8
Address 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh X: Undefined Blank spaces are all reserved. No access is allowed. NOTE: 1. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed. DMA0 Request Source Select Register DMA1 Request Source Select Register DMA2 Request Source Select Register DMA3 Request Source Select Register CRC Data Register CRC Input Register DM0SL DM1SL DM2SL DM3SL CRCD CRCIN 0X00 0000b 0X00 0000b 0X00 0000b 0X00 0000b XXXXh XXh UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART0 Transmit/Receive Mode Register UART0 Baud Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB 00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register Count Source Prescaler Register(1)
SFR Address Map (8)
Register TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC TCSPR Symbol After Reset XXXXh XXXXh XXXXh 00h 00h 00h 00h 00h 00XX 0000b 00XX 0000b 00XX 0000b XXXX XXX0b 0XXX 0000b
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M32C/8A Group Table 4.9
Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh X: Undefined Blank spaces are all reserved. No access is allowed. D/A Control Register DACON XXXX XX00b D/A Register 1 DA1 XXh A/D0 Control Register 2 A/D0 Control Register 3 A/D0 Control Register 0 A/D0 Control Register 1 D/A Register 0 AD0CON2 AD0CON3 AD0CON0 AD0CON1 DA0 XX0X X000b XXXX X000b 00h 00h XXh A/D0 Control Register 4 AD0CON4 XXXX 00XXb A/D0 Register 0 A/D0 Register 1 A/D0 Register 2 A/D0 Register 3 A/D0 Register 4 A/D0 Register 5 A/D0 Register 6 A/D0 Register 7
SFR Address Map (9)
Register AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 Symbol 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh After Reset
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M32C/8A Group Table 4.10
Address 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register(1) Port P10 Direction Register Port P11 Direction Register(1)(2) Port P12 Register(1) Port P13 Register(1) Port P12 Direction Register(1)(2) Port P13 Direction Register(1)(2) P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13 XXh XXh 00h 00h XXh XXh 00X0 0000b 00h XXh XXh 00h XXX0 0000b XXh XXh 00h 00h Function Select Register C Function Select Register A0 Function Select Register A1 Function Select Register B0 Function Select Register B1 Function Select Register A2 Function Select Register A3 Function Select Register B2 Function Select Register B3 PSC PS0 PS1 PSL0 PSL1 PS2 PS3 PSL2 PSL3 00X0 0000b 00h 00h 00h 00h 00X0 0000b 00h 00X0 0000b 00h
SFR Address Map (10)
Register Address Register
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. These registers cannot be used in the 100-pin package. 2. Set to FFh in the 100-pin package.
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M32C/8A Group Table 4.11
Address 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh Port Control Register PCR XXXX XXX0b Pull-Up Control Register 0 Pull-Up Control Register 1 PUR0 PUR1 00h XXXX 0000b Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h Pull-Up Control Register 2 Pull-Up Control Register 3 Pull-Up Control Register 4(1)(3) PUR2 PUR3 PUR4 00h 00h XXXX 0000b Port P14 Register(1) Port P15 Register(1) Port P14 Direction Register(1)(2) Port P15 Direction Register(1)(2)
SFR Address Map (11)
Register P14 P15 PD14 PD15 Address XXh XXh X000 0000b 00h Register
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. These registers cannot be used in the 100-pin package. 2. Set to FFh in the 100-pin package. 3. Set to 00h in the 100-pin package.
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M32C/8A Group
5.
Electrical Characteristics
Table 5.1
Symbol VCC1, VCC2 VCC2 AVCC VI Supply voltage Supply voltage Analog supply voltage Input voltage RESET, CNVSS, BYTE, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1), VREF, XIN P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P7_0, P7_1 VO Output voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P14_0 to 14_6, P15_0 to P15_7(1), XOUT P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P7_0, P7_1 Pd Topr Tstg Power dissipation Operating ambient temperature Storage temperature -40CTopr85C
Absolute Maximum Ratings
Parameter Condition VCC1 = AVCC - VCC1 = AVCC Value -0.3 to 6.0 -0.3 to VCC1 + 0.1 -0.3 to 6.0 -0.3 to VCC1 + 0.3 Unit V V V V
-0.3 to VCC2 + 0.3
-0.3 to 6.0 -0.3 to VCC1 + 0.3 V
-0.3 to VCC2 + 0.3
-0.3 to 6.0 500 -20 to 85/ -40 to 85(2) -65 to 150 mW C C
NOTES: 1. P11 to P15 are provided in the 144-pin package only. 2. Contact a Renesas sales office if temperature range of -40 to 85C is required.
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M32C/8A Group Table 5.2 Recommended Operating Conditions (1) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85C unless otherwise specified)
Parameter Supply voltage (VCC1 VCC2) Analog supply voltage Supply voltage Analog supply voltage 0.8VCC2 Input high "H" P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, voltage P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(2) 0.8VCC1 P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7(1), P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(2), XIN, RESET, CNVSS, BYTE P7_0, P7_1 P0_0 to P0_7, P1_0 to P1_7 (in microprocessor mode) VIL Input low "L" voltage P2_0 to P2_7,P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(2) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7(1), P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(2), XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7 (in microprocessor mode) 0.8VCC1 0.5VCC2 0 Standard Min. 3.0 Typ. 5.0 VCC1 0 0 VCC2 Max. 5.5 Unit V V V V V
Symbol VCC1, VCC2 AVCC VSS AVSS VIH
VCC1
6.0 VCC2 0.2VCC2 V
0
0.2VCC1
0
0.16VCC2
NOTES: 1. VIH and VIL reference for P8_7 apply when P8_7 is used as a programmable input port. It does not apply when P8_7 is used as XCIN. 2. P11 to P15 are provided in the 144-pin package only.
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M32C/8A Group Table 5.3 Recommended Operating Conditions (2) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85C unless otherwise specified
Parameter Peak output high "H" current(2) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3) Standard Min. Typ. Max. -10.0 Unit mA
Symbol
IOH(peak)
IOH(avg)
Average output "H" current(1)
-5.0
mA
IOL(peak)
Peak output "L" current(2)
10.0
mA
IOL(avg)
Average output "L" current(1)
5.0
mA
NOTES: 1. Average output current is the average value within 100 ms. 2. A total IOL(peak) of P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14, and P15 must be 80 mA or less. A total IOL(peak) of P3, P4, P5, P6, P7,P8_0 to P8_4, P12, and P13 must be 80 mA or less. A total IOH(peak) of P0, P1, P2, and P11 must be -40 mA or less. A total IOH(peak) of P8_6 to P8_7, P9, P10, P14, and P15 must be -40 mA or less. A total IOH(peak) of P3, P4, P5, P12, and P13 must be -40 mA or less. A total IOH(peak) of P6, P7, and P8_0 to P8_4 must be -40 mA or less. 3. P11 to P15 are provided in the 144-pin package only.
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Page 35 of 65
M32C/8A Group Table 5.4 Recommended Operating Conditions (3) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85C unless otherwise specified)
Parameter CPU clock frequency (same frequency as f(BCLK)) Main clock input frequency VCC1 = 4.2 to 5.5V VCC1 = 3.0 to 5.5V VCC1 = 4.2 to 5.5V VCC1 = 3.0 to 5.5V f(XCIN) f(Ring) f(VCO) f(PLL) Sub clock frequency On-chip oscillator frequency VCO clock frequency (PLL frequency synthesizer) PLL clock frequency VCC1 = 4.2 to 5.5V VCC1 = 3.0 to 5.5V tsu(PLL) Wait time to stabilize PLL frequency synthesizer VCC1 = 5.0V VCC1 = 3.3V 0.5 20 10 10 Standard Min. 0 0 0 0 32.768 1 Typ. Max. 32 24 32 24 50 2 80 32 24 5 10 Unit MHz MHz MHz MHz kHz MHz MHz MHz MHz ms ms
Symbol f(CPU)
f(XIN)
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M32C/8A Group
VCC1 = VCC2 = 5V
Table 5.5 Electrical Characteristics (1) (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 32 MHz unless otherwise specified)
Parameter Output high "H" voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1) Condition IOH = -5 mA Min. Standard Typ. Max. VCC2 Unit V
Symbol VOH
VCC2 - 2.0
IOH = -5 mA
VCC1 - 2.0
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7 IOH = -200 A VCC2 - 0.3 P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, IOH = -200 A VCC1 - 0.3 P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT High drive capability Low drive capability VOL Output low P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, "L" voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT High drive capability Low drive capability VT+ - VTHysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, ADTRG, CTS0 to CTS4, CLK0 to CLK4, TA0OUT to TA4OUT, NMI, KI0 to KI3, RXD0 to RXD4, SCL0 to SCL4, SDA0 to SDA4 RESET NOTE: 1. P11 to P15 are provided in the 144-pin package only. IOH = -1 mA No load applied No load applied IOL = 5 mA 3.0 2.5 1.6
VCC2
V
VCC1
VCC1
V V V
2.0
V
IOL = 200 A
0.45
V
IOL = 1 mA No load applied No load applied 0.2 0 0
2.0
V V V
1.0
V
0.2
1.8
V
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M32C/8A Group
VCC1 = VCC2 = 5V
Table 5.6 Electrical Characteristics (2) (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 32 MHz unless otherwise specified)
Parameter Input high "H" current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE Condition VI = 5 V Standard Min. Typ. Max. 5.0 Unit A
Symbol IIH
IIL
Input low "L" P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XIN XCIN In stop mode
VI = 0V
-5.0
A
RPULLUP Pull-up resistance
VI = 0V
20
40
167
k
RfXIN RfXCIN VRAM
Feedback resistance Feedback resistance RAM data retention voltage
1.5 10 2.0
M M V
NOTE: 1. P11 to P15 are provided in the 144-pin package only.
Table 5.7
Electrical Characteristics (3) (VCC1 = VCC2 = 5.5 V, VSS = 0 V, Topr = 25C)
Condition ROMless version f(CPU) = 32 MHz f(CPU) = 16 MHz f(CPU) = 8 MHz f(CPU) = f(Ring) In on-chip oscillator low-power consumption mode f(CPU) = 32 kHz In low-power consumption mode f(CPU) = f(Ring) After entering wait mode from on-chip oscillator low-power consumption mode Stop mode (while clock is stopped) Stop mode (while clock is stopped) Topr = 85C Unit Min. Typ. Max. 28 45 mA 16 mA 10 mA 1 mA 25 50 A A Standard
Symbol Parameter ICC Power supply current
0.8
5 50
A A
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M32C/8A Group
VCC1 = VCC2 = 5V
Table 5.8 A/D Conversion Characteristics
(VCC1 = VCC2 = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Topr = -20 to 85C, f(CPU) = 32MHz unless otherwise specified) Symbol - INL Parameter Resolution Integral nonlinearity error Measurement Condition VREF = VCC1 VREF = VCC1 = VCC2 = 5 V AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, ANEX1 External op-amp connection mode DNL - - Differential nonlinearity error Offset error Gain error VREF = VCC1 8 2.06 1.75 0.188 2 0 VCC1 VREF Min. Standard Typ. Max. 10 3 Unit Bits LSB
7 1 3 3 40
LSB LSB LSB LSB k s s s V V
RLADDER Resistor ladder tCONV tCONV tSAMP VREF VIA 10-bit conversion time(1)(2) 8-bit conversion time(1)(2) Sampling time(1) Reference voltage Analog input voltage
NOTES: 1. The value is obtained when AD frequency is at 16 MHz. Keep AD frequency at 16 MHz or less. 2. With using the sample and hold function
Table 5.9
D/A Conversion Characteristics (VCC1 = VCC2 = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Topr = -20 to 85C, f(CPU) = 32MHz unless otherwise specified)
Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current (note 1) 4 10 Measurement Condition Min. Standard Typ. Max. 8 1.0 3 20 1.5 Unit Bits % s k mA
Symbol - - tsu RO IVREF
NOTE: 1. Measured when one D/A converter is used, and the DAi register (i = 0, 1) of the unused D/A converter is set to 00h. The current flown into the resistor ladder in the A/D converter is excluded. IVREF flows even if the VCUT bit in the AD0CON1 register is set to 0 (VREF not connected)
Rev.1.10
Jul 15, 2007
Page 39 of 65
M32C/8A Group
VCC1 = VCC2 = 5V
Table 5.10 Voltage Detection Circuit Electrical Characteristics (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, Topr = 25C unless otherwise specified)
Parameter Vdet4 detection voltage Vdet3 detection voltage Hardware reset 2 hold voltage Hardware reset 2 release voltage VCC1 = 3.0 V to 5.5 V Standard Min. 3.3 Typ. 3.8 3.0 2.0 3.1 Max. 4.4 Unit V V V V
Symbol Vdet4 Vdet3 Vdet3s Vdet3r
NOTES: 1. Vdet4 > Vdet3 2. Vdet3r > Vdet3 is not guaranteed.
Table 5.11
Symbol td(P-R) td(S-R) td(E-A)
Power Supply Timing Characteristics
Parameter Wait time to stabilize internal supply voltage when power-on Wait time to release hardware reset 2 Start-up time for Vdet3 and Vdet4 detection circuit Measurement Condition VCC1 = 3.0 to 5.5 V VCC1 = Vdet3r to 5.5 V VCC1 = 3.0 to 5.5 V 6(1) Standard Min. Typ. Max. 2 20 20 Unit ms ms s
NOTE: 1. When VCC1= 5 V
td(P-R) Wait time to stabilize internal supply voltage when power-on
Recommended operating voltage VCC1 td(P-R) CPU clock
td(S-R) Wait time to release hardware reset 2
Vdet3r VCC1 td(S-R) CPU clock
td(E-A) Start-up time for Vdet3 and Vdet4 detection circuit
VC26, VC27 Vdet3 and Vdet4 detection circuit
Stop
Operating
td(E-A)
Figure 5.1
Power Supply Timing Diagram
Rev.1.10
Jul 15, 2007
Page 40 of 65
M32C/8A Group
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.12
Symbol tc tw(H) tw(L) tr tf
External Clock Input
Parameter External clock input cycle time External clock input high ("H") pulse width External clock input low ("L") pulse width External clock rise time External clock fall time Standard Min. Max. 31.25 13.75 13.75 5 5 Unit ns ns ns ns ns
Table 5.13
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Count Source Input in Event Counter Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. Max. 100 40 40 Unit ns ns ns
Table 5.14
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Gate Signal Input in Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. Max. 400 200 200 Unit ns ns ns
Table 5.15
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. Max. 200 100 100 Unit ns ns ns
Table 5.16
Symbol tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Parameter TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. Max. 100 100 Unit ns ns
Rev.1.10
Jul 15, 2007
Page 41 of 65
M32C/8A Group
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.17
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) i = 0 to 4 TAiOUT input cycle time TAiOUT input high ("H") pulse width TAiOUT input low ("L") pulse width TAiOUT input setup time TAiOUT input hold time
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Parameter Standard Min. Max. 2000 1000 1000 400 400 Unit ns ns ns ns ns
Table 5.18
Symbol tc(TA)
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Parameter TAiIN input cycle time Standard Min. Max. 800 200 200 Unit ns ns ns
tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time
i = 0 to 4
Table 5.19
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Count Source Input in Event Counter Mode)
Parameter TBiIN input cycle time (counted on one edge) TBiIN input high ("H") pulse width (counted on one edge) TBiIN input low ("L") pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input high ("H") pulse width (counted on both edges) TBiIN input low ("L") pulse width (counted on both edges) Standard Min. Max. 100 40 40 200 80 80 Unit ns ns ns ns ns ns
Table 5.20
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. Max. 400 200 200 Unit ns ns ns
Table 5.21
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. Max. 400 200 200 Unit ns ns ns
Rev.1.10
Jul 15, 2007
Page 42 of 65
M32C/8A Group
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.22
Symbol tc(AD) tw(ADL)
A/D Trigger Input
Parameter ADTRG input cycle time (required for trigger) ADTRG input low ("L") pulse width Standard Min. Max. 1000 125 Unit ns ns
Table 5.23
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i=0 to 4
Serial Interface
Parameter CLKi input cycle time CLKi input high ("H") pulse width CLKi input low ("L") pulse width TXDi output delay time TXDi output hold time RXDi input setup time RXDi input hold time 0 30 90 Standard Min. Max. 200 100 100 80 Unit ns ns ns ns ns ns ns
Table 5.24
Symbol tw(INH) tw(INL) i=0 to 5
External Interrupt INTi Input (Edge Sensitive)
Parameter INTi input high ("H") pulse width INTi input low ("L") pulse width Standard Min. Max. 250 250 Unit ns ns
Rev.1.10
Jul 15, 2007
Page 43 of 65
M32C/8A Group
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.25
Symbol
tac1(RD-DB) tac1(AD-DB) tac2(RD-DB) tac2(AD-DB) tsu(DB-BCLK) tsu(RDY-BCLK)
Microprocessor Mode
Parameter Data input access time (RD standard) Data input access time (AD standard, CS standard) Data input access time (RD standard, when accessing a space with the multiplexed bus) Data input access time (AD standard, when accessing a space with the multiplexed bus) Data input setup time RDY input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time 26 26 30 0 0 0 25 Standard Min. Max. (note 1) (note 1) (note 1) (note 1) Unit ns ns ns ns ns ns ns ns ns ns ns
tsu(HOLD-BCLK) HOLD input setup time th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD) td(BCLK-HLDA)
NOTE: 1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD-DB) = 109 x m f(BCLK) x 2 109 x n f(BCLK) 109 x m f(BCLK) x 2 109 x p f(BCLK) x 2 - 35 [ns] (if external bus cycle is a + b, m = (b x 2) + 1)
tac1(AD-DB) =
- 35 [ns] (if external bus cycle is a + b, n = a + b)
tac2(RD-DB) =
- 35 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
tac2(AD-DB) =
- 35 [ns] (if external bus cycle is a + b, p = {(a + b - 1) x 2} + 1)
Rev.1.10
Jul 15, 2007
Page 44 of 65
M32C/8A Group
VCC1 = VCC2 = 5V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.26
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR)
Microprocessor Mode (when accessing external memory space)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD Address output hold time (WR standard)(3) standard)(3) -3 0 (note 1) 18 -3 0 See Figure 5.2 (note 1) 18 -5 18 -5 (note 2) (note 1) (note 2) standard)(3) standard)(3) Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD Chip-select signal output hold time (WR RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard)(3) WR output width
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(WR-DB) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 - 10 [ns]
th(WR-AD) =
- 10 [ns]
th(WR-CS) =
- 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations.
td(DB-WR) = 109 x m f(BCLK) 109 x n f(BCLK) x 2 - 20 [ns] (if external bus cycle is a + b, m = b)
tw(WR)
=
- 15 [ns] (if external bus cycle is a + b, n = (b x 2) - 1)
3. tc [ns] is added when recovery cycle is inserted.
Rev.1.10
Jul 15, 2007
Page 45 of 65
M32C/8A Group
VCC1 = VCC2 = 5V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.27
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) tdz(RD-AD)
Microprocessor Mode (when accessing external memory space with multiplexed bus)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD Address output hold time (WR standard)(5) standard)(5) -3 (note 1) (note 1) 18 -3 (note 1) (note 1) 18 See Figure 5.2 -5 18 -5 (note 2) (note 1) 18 -2 (note 3) (note 4) 8 standard)(5) standard)(5) Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD Chip-select signal output hold time (WR RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard)(5) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (address standard) ALE signal output hold time (address standard) Address output float start time
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(RD-AD) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 - 10 [ns]
th(WR-AD) =
- 10 [ns]
th(RD-CS)
=
- 10 [ns]
th(WR-CS) =
- 10 [ns]
th(WR-DB) =
- 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(DB-WR) = 109 x m f(BCLK) x 2 109 x n f(BCLK) x 2 109 x n f(BCLK) x 2 - 25 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(AD-ALE) = - 20 [ns] (if external bus cycle is a + b, n = a)
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
th(ALE-AD) = - 10 [ns] (if external bus cycle is a + b, n = a)
5. tc [ns] is added when recovery cycle is inserted.
Rev.1.10
Jul 15, 2007
Page 46 of 65
M32C/8A Group
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
30 pF
Note 1
NOTE: 1. P11 to P15 are provided in the 144-pin package only.
Figure 5.2
P0 to P15 Measurement Circuit
Rev.1.10
Jul 15, 2007
Page 47 of 65
M32C/8A Group
VCC1=VCC2=5V
tc
XIN input
tr
tw(H) tc(TA) tw(TAH)
tf
tw(L)
TAiIN input
tw(TAL) tc(UP) tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input (counter increment/ decrement select input) In event counter mode TAiIN input (count on falling edge) TAiIN input (count on rising edge) In event counter mode with two-phase pulse TAiIN input
tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
th(TIN-UP)
tsu(UP-TIN)
tc(TA)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB) tw(TBH)
TBiIN input
tw(TBL) tc(AD) tw(ADL)
ADTRG input
tc(CK) tw(CKH)
CLKi
tw(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi
tw(INL)
INTi input NMI input
2 CPU clock cycles + 300 ns or more ("L" width)
tw(INH)
2 CPU clock cycles + 300 ns or more
Figure 5.3 Rev.1.10
VCC1 = VCC2 = 5 V Timing Diagram (1) Page 48 of 65
Jul 15, 2007
M32C/8A Group
VCC1=VCC2=5V
Microprocessor Mode
BCLK RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
(Multiplexed bus)
RD
WR, WRL, WRH
(Multiplexed bus)
RDY Input
tsu(RDY-BCLK) th(BCLK-RDY)
BCLK
tsu(HOLD-BCLK) th(BCLK-HOLD)
HOLD Input
HLDA Output
td(BCLK-HLDA) td(BCLK-HLDA) Hi-Z
P0, P1, P2, P3, P4, P5_0 to P5_2
Measurement Conditions -VCC1 = VCC2 = 4.2 to 5.5 V -Input high and low voltage: VIH = 4.0 V, VIL = 1.0 V -Output high and low voltage: VOH = 2.5 V, VOL = 2.5 V
Figure 5.4
VCC1 = VCC2 = 5 V Timing Diagram (2)
Rev.1.10
Jul 15, 2007
Page 49 of 65
M32C/8A Group
Microprocessor Mode (when accessing an external memory space)
Read Timing (1 + 1 Bus Cycle)
BCLK
VCC1=VCC2=5V
td(BCLK-CS)
18ns.max(1)
th(BCLK-CS)
-3ns.min
CSi
tcyc
th(RD-CS)
0ns.min
td(BCLK-AD)
18ns.max(1)
th(BCLK-AD)
-3ns.min
ADi BHE
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
tac1(RD-DB)(2) tac1(AD-DB)(2)
DB
th(BCLK-RD)
-5ns.min
Hi-Z
tsu(DB-BCLK)
26ns.min(1)
th(RD-DB)
0ns.min
NOTES: 1. Values guaranteed only when the MCU is used stand-alone. A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK). 2. Varies with operation frequency: tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) + 1) tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle a + b, n = a + b)
Write Timing (1 + 1 Bus Cycle)
BCLK
td(BCLK-CS)
18ns.max
th(BCLK-CS)
-3ns.min
CSi
tcyc
td(BCLK-AD)
18ns.max
th(WR-CS)(3)
th(BCLK-AD)
-3ns.min
ADi BHE
td(BCLK-WR)
18ns.max
th(WR-AD)(3) tw(WR)(3)
WR,WRL,WRH
th(BCLK-WR)
-5ns.min
td(DB-WR)(3)
DBi
th(WR-DB)(3)
NOTES: Measurement Conditions: 3. Varies with operation frequency: - VCC1 = VCC2 = 4.2 to 5.5 V td(DB-WR) = (tcyc x m - 20) ns.min - Input high and low voltage: VIH = 2.5 V, VIL = 0.8 V (if external bus cycle a + b, m = b) - Output high and low voltage: VOH = 2.0 V, VOL = 0.8 V th(WR-DB) = (tcyc / 2 - 10) ns.min th(WR-AD) = (tcyc / 2 - 10) ns.min th(WR-CS) = (tcyc / 2 - 10) ns.min 109 tw(WR) = (tcyc / 2 x n - 15) ns.min tcyc= f(BCLK) (if external bus cycle a + b, n = (b x 2) - 1)
Figure 5.5 Rev.1.10
VCC1 = VCC2 = 5 V Timing Diagram (3) Page 50 of 65
Jul 15, 2007
M32C/8A Group
Microprocessor Mode (when accessing an external memory space with the multiplexed bus)
Read Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
VCC1=VCC2=5V
ALE
td(BCLK-CS) 18ns.max
tcyc th(RD-CS)(1)
th(BCLK-CS) -3ns.min
CSi
td(AD-ALE)(1) th(ALE-AD)(1)
tsu(DB-BCLK) 26ns.min
ADi /DBi
td(BCLK-AD) 18ns.max
Address
tdz(RD-AD) 8ns.max tac2(RD-DB)(1)
Data input
Address
th(RD-DB) 0ns.min th(BCLK-AD) -3ns.min
ADi BHE
tac2(AD-DB)(1) th(RD-AD)(1) td(BCLK-RD) 18ns.max th(BCLK-RD) -5ns.min
RD
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b, n = a) th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) - 1) tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a + b, p = {(a + b - 1) x 2} + 1)
Write Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
ALE
td(BCLK-CS) 18ns.max tcyc th(WR-CS)(2) -3ns.min
th(BCLK-CS)
CSi
td(AD-ALE)(2) th(ALE-AD)(2)
ADi /DBi
td(BCLK-AD) 18ns.max
Address
Data output
td(DB-WR)(2) th(WR-DB)(2)
Address
ADi BHE
td(BCLK-WR) 18ns.max th(BCLK-WR) -5ns.min
th(BCLK-AD) -3ns.min
WR,WRL,WRH
th(WR-AD)(2)
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b, n = a) th(WR-AD) = (tcyc / 2 - 10) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min th(WR-DB) = (tcyc / 2 - 10) ns.min td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a + b, m = (b x 2) - 1) Measurement Conditions: 109 - VCC1 = VCC2 = 4.2 to 5.5 V tcyc= - Input high and low voltage VIH = 2.5 V, VIL = 0.8 V f(BCLK) - Output high and low voltage VOH = 2.0 V, VOL = 0.8 V
Figure 5.6 Rev.1.10
VCC1 = VCC2 = 5 V Timing Diagram (4) Page 51 of 65
Jul 15, 2007
M32C/8A Group
VCC1 = VCC2 = 3.3 V
Table 5.28 Electrical Characteristics (1)
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 24 MHz unless otherwise specified) Symbol VOH Output high "H" voltage Parameter P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT High drive capability Low drive capability VOL Output low P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, "L" voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT High drive capability Low drive capability VT+ - VTHysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, ADTRG, CTS0 to CTS4, CLK0 to CLK4, TA0OUT to TA4OUT, NMI, KI0 to KI3, RXD0 to RXD4, SCL0 to SCL4, SDA0 to SDA4 RESET NOTE: 1. P11 to P15 are provided in the 144-pin package only. IOH = -0.1 mA No load applied No load applied IOL = 1 mA Condition IOH = -1 mA Min. Standard Typ. Max. VCC2 Unit V
VCC2 - 0.6
VCC1 - 0.6
VCC1
2.7 2.5 1.6
VCC1
V V V
0.5
V
IOL = 0.1 mA No load applied No load applied 0.2 0 0
0.5
V V V
1.0
V
0.2
1.8
V
Rev.1.10
Jul 15, 2007
Page 52 of 65
M32C/8A Group
VCC1 = VCC2 = 3.3 V
Table 5.29 Electrical Characteristics (2) (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 24 MHz unless otherwise specified)
Parameter Input high P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, "H" current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE Input low "L" current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XIN XCIN In stop mode 2.0 Condition VI = 3 V Standard Min. Typ. Max. 4.0 Unit A
Symbol IIH
IIL
VI = 0V
-4.0
A
RPULLUP Pull-up resistance
VI=0V
40
70
500
k
RfXIN RfXCIN VRAM
Feedback resistance Feedback resistance RAM data retention voltage
3.0 20.0
M M V
NOTE: 1. P11 to P15 are provided in the 144-pin package only. Table 5.30
Electrical Characteristics (3) (VCC1 = VCC2 = 3.3 V, VSS = 0 V, Topr = 25C)
Condition ROMless version f(CPU) = 24 MHz f(CPU) = 16 MHz f(CPU) = 8 MHz f(CPU) = f(Ring) In on-chip oscillator low-power consumption mode f(CPU) = 32 kHz In low-power consumption mode f(CPU) = f(Ring) After entering wait mode from on-chip oscillator low-power consumption mode Stop mode (while clock is stopped) Stop mode (while clock is stopped) Topr = 85C Unit Min. Typ. Max. 22 33 mA 15 mA 9 mA 1 mA 25 45 A A Standard
Symbol Parameter ICC Power supply current
0.8
5 50
A A
Rev.1.10
Jul 15, 2007
Page 53 of 65
M32C/8A Group
VCC1 = VCC2 = 3.3 V
Table 5.31 A/D Conversion Characteristics (VCC1 = VCC2 = AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, Topr = -20 to 85C, f(CPU) = 24MHz unless otherwise specified)
Parameter Resolution Integral nonlinearity error (8-bit) Differential nonlinearity error (8-bit) Offset error (8-bit) Gain error (8-bit) VREF = VCC1 time(1)(2) 8 4.9 3 0 VCC1 VREF Measurement Condition VREF = VCC1 VREF = VCC1 = VCC2 = 3.3 V Standard Min. Typ. Max. 10 2 1 2 2 40 Unit Bits LSB LSB LSB LSB k s V V
Symbol - INL DNL - -
RLADDER Resistor ladder tCONV VREF VIA 8-bit conversion
Reference voltage Analog input voltage
NOTES: 1. The value when AD frequency is at 10 MHz. Keep AD frequency at 10 MHz or less. If f(CPU) (=fAD) is 24 MHz, divide f(CPU) by 3 to make it 8 MHz. The conversion time in this case is 6.1 s. 2. S&H not available.
Table 5.32
D/A Conversion Characteristics (VCC1 = VCC2 = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V at Topr = -20 to 85C, f(CPU) = 24MHz unless otherwise specified)
Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current (note 1) 4 10 Measurement Condition Standard Min. Typ. Max. 8 1.0 3 20 1.0 Unit Bits % s k mA
Symbol - - tsu RO IVREF
NOTE: 1. Measurement when one D/A converter is used, and the DAi register (i = 0, 1) of the unused D/A converter is set to 00h. The current flown into the resistor ladder in the A/D converter is excluded. IVREF flows even if VCUT bit in the AD0CON1 register is set to 0 (VREF not connected)
Rev.1.10
Jul 15, 2007
Page 54 of 65
M32C/8A Group
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.33
Symbol tc tw(H) tw(L) tr tf
External Clock Input
Parameter External clock input cycle time External clock input high ("H") pulse width External clock input low ("L") pulse width External clock rise time External clock fall time Standard Min. Max. 41 18 18 5 5 Unit ns ns ns ns ns
Table 5.34
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Count Source Input in Event Counter Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. Max. 100 40 40 Unit ns ns ns
Table 5.35
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Gate Signal Input in Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. Max. 400 200 200 Unit ns ns ns
Table 5.36
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. Max. 200 100 100 Unit ns ns ns
Table 5.37
Symbol tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Parameter TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. Max. 100 100 Unit ns ns
Rev.1.10
Jul 15, 2007
Page 55 of 65
M32C/8A Group
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.38
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) i = 0 to 4 TAiOUT input cycle time TAiOUT input high ("H") pulse width TAiOUT input low ("L") pulse width TAiOUT input setup time TAiOUT input hold time
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Parameter Standard Min. Max. 2000 1000 1000 400 400 Unit ns ns ns ns ns
Table 5.39
Symbol tc(TA)
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Parameter TAiIN input cycle time Standard Min. Max. 2 500 500 Unit s ns ns
tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time
i = 0 to 4
Table 5.40
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Count Source Input in Event Counter Mode)
Parameter TBiIN input cycle time (counted on one edge) TBiIN input high ("H") pulse width (counted on one edge) TBiIN input low ("L") pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input high ("H") pulse width (counted on both edges) TBiIN input low ("L") pulse width (counted on both edges) Standard Min. Max. 100 40 40 200 80 80 Unit ns ns ns ns ns ns
Table 5.41
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. Max. 400 200 200 Unit ns ns ns
Table 5.42
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. Max. 400 200 200 Unit ns ns ns
Rev.1.10
Jul 15, 2007
Page 56 of 65
M32C/8A Group
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.43
Symbol tc(AD) tw(ADL)
A/D Trigger Input
Parameter ADTRG input cycle time (required for trigger) ADTRG input low ("L") pulse width Standard Min. Max. 1000 125 Unit ns ns
Table 5.44
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i=0 to 4
Serial Interface
Parameter CLKi input cycle time CLKi input high ("H") pulse width CLKi input low ("L") pulse width TXDi output delay time TXDi output hold time RXDi input setup time RXDi input hold time 0 30 90 Standard Min. Max. 200 100 100 80 Unit ns ns ns ns ns ns ns
Table 5.45
Symbol tw(INH) tw(INL) i=0 to 5
External Interrupt INTi Input (Edge Sensitive)
Parameter INTi input high ("H") pulse width INTi input low ("L") pulse width Standard Min. Max. 250 250 Unit ns ns
Rev.1.10
Jul 15, 2007
Page 57 of 65
M32C/8A Group
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.46
Symbol
tac1(RD-DB) tac1(AD-DB) tac2(RD-DB) tac2(AD-DB) tsu(DB-BCLK) tsu(RDY-BCLK)
Microprocessor Mode
Parameter Data input access time (RD standard) Data input access time (AD standard, CS standard) Data input access time (RD standard, when accessing a space with the multiplexed bus) Data input access time (AD standard, when accessing a space with the multiplexed bus) Data input setup time RDY input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time 30 40 60 0 0 0 25 Standard Min. Max. (note 1) (note 1) (note 1) (note 1) Unit ns ns ns ns ns ns ns ns ns ns ns
tsu(HOLD-BCLK) HOLD input setup time th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD) td(BCLK-HLDA)
NOTE: 1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD-DB) = 109 x m f(BCLK) x 2 109 x n f(BCLK) 109 x m f(BCLK) x 2 109 x p f(BCLK) x 2 - 35 [ns] (if external bus cycle is a + b, m = (b x 2) + 1)
tac1(AD-DB) =
- 35 [ns] (if external bus cycle is a + b, n = a + b)
tac2(RD-DB) =
- 35 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
tac2(AD-DB) =
- 35 [ns] (if external bus cycle is a + b, p = {(a + b - 1) x 2} + 1)
Rev.1.10
Jul 15, 2007
Page 58 of 65
M32C/8A Group
VCC1 = VCC2 = 3.3 V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.47
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR)
Microprocessor Mode (when accessing external memory space)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD Address output hold time (WR standard)(3) standard)(3) 0 0 (note 1) 18 0 0 See Figure 5.2 (note 1) 18 -3 18 0 (note 2) (note 1) (note 2) standard)(3) standard)(3) Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD Chip-select signal output hold time (WR RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard)(3) WR output width
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(WR-DB) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 - 20 [ns]
th(WR-AD) =
- 10 [ns]
th(WR-CS) =
- 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations.
td(DB-WR) = 109 x m f(BCLK) 109 x n f(BCLK) x 2 - 20 [ns] (if external bus cycle is a + b, m = b)
tw(WR)
=
- 15 [ns] (if external bus cycle is a + b, n = (b x 2) - 1)
3. tc [ns] is added when recovery cycle is inserted.
Rev.1.10
Jul 15, 2007
Page 59 of 65
M32C/8A Group
VCC1 = VCC2 = 3.3 V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified)
Table 5.48
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) tdz(RD-AD)
Microprocessor Mode (when accessing external memory space with multiplexed bus)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard)(5) Address output hold time (WR standard)(5) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD standard)(5) Chip-select signal output hold time (WR standard)(5) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard)(5) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (address standard) ALE signal output hold time (address standard) Address output float start time -2 (note 3) (note 4) 8 0 (note 2) (note 1) 18 See Figure 5.2 -3 18 0 (note 1) (note 1) 18 0 (note 1) (note 1) 18 Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(RD-AD) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 - 10 [ns]
th(WR-AD) =
- 10 [ns]
th(RD-CS)
=
- 10 [ns]
th(WR-CS) =
- 10 [ns]
th(WR-DB) =
- 20 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(DB-WR) = 109 x m f(BCLK) x 2 109 x n f(BCLK) x 2 109 x n f(BCLK) x 2 - 25 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(AD-ALE) = - 20 [ns] (if external bus cycle is a + b, n = a)
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
th(ALE-AD) = - 10 [ns] (if external bus cycle is a + b, n = a)
5. tc [ns] is added when recovery cycle is inserted.
Rev.1.10
Jul 15, 2007
Page 60 of 65
M32C/8A Group
VCC1=VCC2=3.3V
tc
XIN input
tr
tw(H) tc(TA) tw(TAH)
tf
tw(L)
TAiIN input
tw(TAL) tc(UP) tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input (counter increment/ decrement select input) In event counter mode TAiIN input (count on falling edge) TAiIN input (count on rising edge) In event counter mode with two-phase pulse TAiIN input
tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
th(TIN-UP)
tsu(UP-TIN)
tc(TA)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB) tw(TBH)
TBiIN input
tw(TBL) tc(AD) tw(ADL)
ADTRG input
tc(CK) tw(CKH)
CLKi
tw(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi
tw(INL)
INTi input NMI input
2 CPU clock cycles + 300 ns or more ("L" width)
tw(INH)
2 CPU clock cycles + 300 ns or more
Figure 5.7 Rev.1.10
VCC1 = VCC2 = 3.3 V Timing Diagram (1) Page 61 of 65
Jul 15, 2007
M32C/8A Group
VCC1=VCC2=3.3V
Microprocessor Mode
BCLK RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
(Multiplexed bus)
RD
WR, WRL, WRH
(Multiplexed bus)
RDY Input
tsu(RDY-BCLK) th(BCLK-RDY)
BCLK
tsu(HOLD-BCLK) th(BCLK-HOLD)
HOLD Input
HLDA Output
td(BCLK-HLDA) td(BCLK-HLDA) Hi-Z
P0, P1, P2, P3, P4, P5_0 to P5_2
Measurement Conditions -VCC1 = VCC2 = 3.0 to 3.6 V -Input high and low voltage: VIH = 2.4 V, VIL = 0.6 V -Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V
Figure 5.8
VCC1 = VCC2 = 3.3 V Timing Diagram (2)
Rev.1.10
Jul 15, 2007
Page 62 of 65
M32C/8A Group
Microprocessor Mode (when accessing an external memory space)
Read Timing (1 + 1 Bus Cycle)
BCLK
VCC1=VCC2=3.3V
td(BCLK-CS)
18ns.max(1)
th(BCLK-CS)
0ns.min
CSi
tcyc
th(RD-CS)
0ns.min
td(BCLK-AD)
18ns.max(1)
th(BCLK-AD)
0ns.min
ADi BHE
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
tac1(RD-DB)(2) tac1(AD-DB)(2)
DB
th(BCLK-RD)
-3ns.min
Hi-Z
tsu(DB-BCLK)
30ns.min(1)
th(RD-DB)
0ns.min
NOTES: 1. Values guaranteed only when the MCU is used stand-alone. A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK). 2. Varies with operation frequency: tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) + 1) tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle a + b, n = a + b)
Write Timing (1 + 1 Bus Cycle)
BCLK
td(BCLK-CS)
18ns.max
0ns.min
th(BCLK-CS)
CSi
tcyc
td(BCLK-AD)
18ns.max
th(WR-CS)(3)
0ns.min
th(BCLK-AD)
ADi BHE
td(BCLK-WR)
18ns.max
th(WR-AD)(3) tw(WR)(3)
WR,WRL,WRH
th(BCLK-WR)
0ns.min
td(DB-WR)(3)
DBi
th(WR-DB)(3)
NOTES: Measurement Conditions: 3. Varies with operation frequency: - VCC1 = VCC2 = 3.0 to 3.6 V td(DB-WR) = (tcyc x m - 20) ns.min - Input high and low voltage: VIH = 1.5 V, VIL = 0.5 V (if external bus cycle a + b, m = b) - Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V th(WR-DB) = (tcyc / 2 - 20) ns.min th(WR-AD) = (tcyc / 2 - 10) ns.min th(WR-CS) = (tcyc / 2 - 10) ns.min 109 tw(WR) = (tcyc / 2 x n - 15) ns.min tcyc= f(BCLK) (if external bus cycle a + b, n = (b x 2) - 1)
Figure 5.9 Rev.1.10
VCC1 = VCC2 = 3.3 V Timing Diagram (3) Page 63 of 65
Jul 15, 2007
M32C/8A Group
Microprocessor Mode (when accessing an external memory space with the multiplexed bus)
Read Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
VCC1=VCC2=3.3V
ALE
td(BCLK-CS) 18ns.max
tcyc th(RD-CS)(1)
th(BCLK-CS) 0ns.min
CSi
td(AD-ALE)(1) th(ALE-AD)(1)
tsu(DB-BCLK) 30ns.min
ADi /DBi
td(BCLK-AD) 18ns.max
Address
tdz(RD-AD) 8ns.max tac2(RD-DB)(1)
Data input
Address
th(RD-DB) 0ns.min th(BCLK-AD) 0ns.min
ADi BHE
tac2(AD-DB)(1) th(RD-AD)(1) td(BCLK-RD) 18ns.max th(BCLK-RD) -3ns.min
RD
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b, n = a) th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) - 1) tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a + b, p = {(a + b - 1) x 2} + 1)
Write Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
ALE
td(BCLK-CS) 18ns.max tcyc th(WR-CS)(2) 0ns.min
th(BCLK-CS)
CSi
td(AD-ALE)(2) th(ALE-AD)(2)
ADi /DBi
td(BCLK-AD) 18ns.max
Address
Data output
td(DB-WR)(2) th(WR-DB)(2)
Address
ADi BHE
td(BCLK-WR) 18ns.max th(BCLK-WR) 0ns.min
th(BCLK-AD) 0ns.min
WR,WRL,WRH
th(WR-AD)(2)
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b, n = a) th(WR-AD) = (tcyc / 2 - 10) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min th(WR-DB) = (tcyc / 2 - 20) ns.min td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a + b, m = (b x 2) - 1) Measurement Conditions: 109 - VCC1 = VCC2 = 3.0 to 3.6 V tcyc= - Input high and low voltage VIH = 1.5 V, VIL = 0.5 V f(BCLK) - Output high and low voltage VOH = 1.5 V, VOL = 1.5 V
Figure 5.10 Rev.1.10
VCC1 = VCC2 = 3.3 V Timing Diagram (4) Page 64 of 65
Jul 15, 2007
M32C/8A Group
Appendix 1. Package Dimensions
JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g
HD *1 108 D 73 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1
109
72
c1 HE E
c
Reference Symbol
*2
Dimension in Millimeters
Terminal cross section
1 ZD
A2
A
36 Index mark F
ZE
144
37
L L1
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
*3 e y
bp
x
Detail F
Min Nom Max 19.9 20.0 20.1 19.9 20.0 20.1 1.4 21.8 22.0 22.2 21.8 22.0 22.2 1.7 0.05 0.1 0.15 0.17 0.22 0.27 0.20 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.10 1.25 1.25 0.35 0.5 0.65 1.0
JEITA Package Code P-LQFP100-14x14-0.50
RENESAS Code PLQP0100KB-A
Previous Code 100P6Q-A / FP-100U / FP-100UV
MASS[Typ.] 0.6g
HD *1 D
75
51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
76
50
A1
bp b1
HE
E
c
Reference Dimension in Millimeters Symbol
*2
c1
c
Terminal cross section
1 Index mark ZD
25 F
ZE
100
26
A2
A
D E A2 HD HE A A1 bp b1 c c1
c
A1
y e
*3
bp
L L1 Detail F
x
e x y ZD ZE L L1
Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 8 0 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0
Rev.1.10
Jul 15, 2007
Page 65 of 65
REVISION HISTORY
Rev. Rev.1.00 Rev.1.10 Date Apr 01, 2007 Jul 15, 2007 6
M32C/8A Group Datasheet
Description
Page - First Edition issued - 144-pin package added - Table "Product list" revised
Summary
A-1
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
(c) 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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